1. Field of the Invention
The present invention generally relates to a phase rotator device and to a data recovery receiver incorporating the phase rotator device, e.g. for use in digital data communications based on high speed wire link technology for high-speed digital switches involving clock and data recovery (CDR). More specifically, the invention concerns a phase rotator capable of producing a controlled phase shift, e.g. on a multiphase input clock signal, and a data recovery receiver incorporating such a phase rotator in a feedback control loop for synchronously tracking level transitions in a high-speed data stream.
2. Description of the Related Art
When performing CDR, conventional systems track possible phase variations in an incoming data stream in order to ensure that all the information-carrying level transitions can be followed synchronously. To this end, the incoming data signal stream is processed by a CDR receiver which is capable of phase agility.
Now the speed of switches, especially in the context of internet switches, is currently developing fast. With this growth in speed, a problem now resides at the level of link technology, which is becoming the limiting factor for feeding data into and out of a digital core. Indeed, a digital core can comprise up to one hundred or more data links on one single digital chip.
In addition, such a chip performs digital functions which consume tens of Watts at few volts of power supply voltage, which means that tens of amps flow into and out of the chip at a few nano-seconds of cycle time. This creates a very noisy environment in terms of power supply swing, substrate noise, etc.
Under these conditions, there is a need for circuit structures that can perform CDR on the incoming data stream with a satisfactory bit error rate while being able to handle very high frequencies, e.g. up to 2.5 GHertz or more.
CDR circuit structures known in the art can be divided into two main categories: conventional analog-based phase-locked loop (PLL) feedback CDR receivers and digital oversampling receivers.
FIG. 1 is a simplified block diagram showing a typical analog PLL feedback CDR receiver circuit. The circuit 2 has an input terminal 4 which receives a data input signal Datain that may be transmitted in differential form. The input is divided into first and second branches b1 and b2, respectively, for effecting a clock recovery and a data recovery.
The first branch b1 forms an input to a PLL circuit 6. The latter classically comprises a phase comparator 8 having two phase comparison inputs φa and φb, a low-pass filter 10 and an analog voltage controlled oscillator (VCO) 12. The phase detector 8 receives the input data signal Datain and a quadrature output (Q) from the VCO at its respective phase comparison inputs φa and φb, and outputs a voltage control signal to the VCO 12 via the low pass filter 10. In this way, the VCO is forced to track the frequency of the incoming data input signal by maintaining a zero phase difference between the phase comparison inputs φa and φb. The low pass filter ensures that the feedback loop containing the VCO 12 is kept within the frequency response of the latter. In the example, the clock recovery signal (clock out) is taken out from an in-phase output (I) of the VCO for optimally sampling the data.
The above in-phase signal from the VCO 12 also serves as a sampling clock signal for a data sampling circuit 14, the data input of which receives the data input signal from the second branch b2. The data sampling circuit thereby produces at an output terminal 16 the data output signal Dataout corresponding to the data input signal sampled at the instantaneous recovered clock frequency.
Thus, the output phase of the VCO 12 is controlled to match the optimum sampling point position by means of the PLL feedback control loop. Feedback control loops in general have a bandwidth limitation in the region of one tenth of the feedback frequency due to stability problems.
The above approach is the most commonly used owing to its simple structure. It served well in the past in applications which did not require very high frequencies and used only one channel, without relying on digital oversampling techniques.
FIG. 2 is a simplified block diagram showing a digital oversampling feed forward receiver with ‘a posteriori decision’. In this circuit, the incoming data stream is oversampled (i.e., sampled more than once per period of the input signal) to determine the data transition positions, also known as the edges of the data. The edge information serves as a basis for selecting, or “phase picking”, the best sample as data value in an “a posteriori step.”
The circuit 20 comprises a PLL unit 22 which delivers a number n of clock output phases nφClock each having a common frequency corresponding to that of a reference signal Finref, but at different phases relative to each other. The PLL unit is classically constructed from a multi-phase output VCO 24 connected to a PLL feedback loop 26 which receives the reference frequency signal Finref. The latter is made to correspond as closely as possible to the frequency of the incoming data stream Datain. The PLL feedback loop 26 generally includes a phase comparator for comparing an output phase of the VCO 24 with the phase of the reference frequency Finref, the comparison output being fed back to the control input of the VCO via a low-pass filter.
The n different phases from the VCO 24 are supplied as clock signals to respective ones of a set of n oversampling latches 28. The n oversampling latches each receive the signal Datain in from the incoming data stream. Thus, for each period of the incoming data, the latches 28 sample different points of the signal waveform.
The n thus-sampled signals are supplied to what is known as a phase picking engine 30, whose function is to determine the position of the edge transitions in the incoming data on the basis of these sampled values.
The phase picking engine 30 shown in FIG. 2 comprises a digital noise matched low-pass filter 32 forming an input stage for the n sampled values. After the filter stage, the n sampled values are supplied to respective data inputs of a digital edge detector 34 and to an n-to-1 multiplexer 36 which delivers the recovered data Dataout at a data output terminal 16. The digital edge detector 34 effectively identifies the later one of two chronologically successive samples that marks a transition in the incoming data signal, and commands the multiplexer 36 to designate that sample point as the basis for establishing the recovered data output Dataout. This sample (referred to as the best sample) is thus selected as the data value for a particular signal period in an a posteriori step.
The above circuit implements a feed forward method with no inherent bandwidth limitation and potential non-causal data processing. Digital circuits after the sampling stage (e.g. a bit shifter and byte FIFOS) can take care of wrap-around effects occurring when there is a slight offset in the input data rate and the reference frequency.
Both of the above types of CDR receivers have their advantages and disadvantages.
The approach described with reference to FIG. 1 is based on an analog control of the clock frequency and has an inherently limited jitter tracking bandwidth, but unlimited frequency tracking capability.
The approach described with reference to FIG. 2 is purely digital and makes it possible to track jitter frequencies up to the bit rate, but only with limited jitter amplitude. There is no feedback from the sampling logic to the clock-generating PLL. Therefore, one PLL can serve several receivers.
The positive and negative points of the above-described CDR systems are summarised in Table I below. It may be noticed that the table entries are somewhat orthogonal for the two approaches, i.e. an advantage of one approach is a disadvantage of the other.
TABLE Icomparison of merits between analog and digital CDR receivers.Analog PLL-based CDRsAdvantages:unlimited jitter amplitude tracking;simple structure;only one sample has to be processed.Disadvantages:inherent jitter tracking bandwidth limitation;analog control;no averaging possible;one PLL per channel required.Oversampling-based digital CDRsAdvantages:jitter suppression up to bit rate frequency;digital control;‘a posteriori’ data/edge analysis;single PLL for several channels.Disadvantages:limited jitter amplitude tracking;complex structure;multiphase oscillator required.